The present invention relates to improvement of a delay adjusting device and an improved delay adjusting method adopted for adjusting different delay times of plural transmission lines in rapid signal transmission where plural signals are simultaneously transmitted through the plural transmission lines.
In general, plural signal transmission lines have mutually different signal transmission delay times, and hence, skew is caused between transmitted signals. For example, when plural data are transmitted to one and the same receiver part, there arises a time difference in the receipt of these data at the receiver part. Also, when the same signal (such as a clock signal) is transmitted to plural receiver parts, there arises a time difference in the receipt of the signal at the respective receiver parts. Such skew is caused both in the case where a signal is transmitted within one LSI and in the case where a signal is transmitted between plural LSIs. The occurrence of the skew can lead to malfunction of the LSI.
Therefore, as is disclosed in, for example, Japanese Laid-Open Patent Publication No. 7-73118, a synchronous circuit is conventionally provided, so that, when a phase shift is caused between signals received through different transmission lines, the phase shift between the signals can be absorbed and adjusted by using a signal on the latest transmission line as a reference and providing the other transmission lines with predetermined delay devices.
As another conventional technique, as is disclosed in, for example, Japanese Laid-Open Patent Publication No. 6-54016, in the case where plural data are transmitted by using transmission lines in the same number as the number of the data, timing of fetching these data by receiver parts (flip-flops), namely, input timing of a clock signal to these flip-flops, is made adjustable. Thus, a clock signal is input after receiving all the data, thereby allowing the plural data to be received at the same time at the receiver parts.
As a result of recent increase of the operation speed of LSIs and the like, some LSIs require rapid signal transmission with a transmission rate of 550 MB/sec. (namely, 250 MHZ) or more in parallel data transmission using plural transmission lines. For example, in signal transmission with a transmission rate of 500 MHZ, one cycle has a length of 2 nanoseconds or less.
However, in LSIs and the like operated at such a high speed, any of the aforementioned conventional techniques cannot be adopted for adjusting a phase shift due to the signal skew for the following reason:
In the former conventional technique, a phase difference between waveforms of signals received at plural receiver parts is detected. Therefore, with one cycle of a clock signal indicated as T, when a phase shift between waveforms of received signals is smaller than T/2, the phase shift can be adjusted. However, in three signals A, B and C as is shown in FIG. 14(a), when a phase shift between the signals A and C is T+xcfx842, namely, larger than T/2, the signal C is adjusted to be shifted from the signal A by one cycle T as is shown in FIG. 14(b). When there is a length difference of, for example, 10 cm between the transmission lines, a phase shift of 2 nanoseconds is caused with a load of 40 pF, and this phase shift exceeds one cycle in the aforementioned signal transmission with a rate of 500 MHZ. Thus, it would be understood that such a situation can be easily presumed.
Alternatively, in the latter conventional technique, the receiving timing of the clock signal is adjusted so that the clock signal can be received after receiving the plural data. Therefore, in the case where a phase shift of any of the data exceeds one cycle, at the receipt of this data, the other data can be changed to have values of a subsequent cycle. Accordingly, the data fetching timing of the flip-flops cannot be adjusted to be simultaneous. In this manner, it is impossible to overcome the problem of the signal skew in high speed LSIs and the like by using any of the aforementioned two conventional techniques.
The object of the invention is, in signal transmission by using plural transmission lines in a rapidly operated LSI or the like where a signal is simultaneously transmitted through the transmission lines, adjusting phase shifts between signals on all the transmission lines satisfactorily even when the signal transmission delay time of any of the transmission lines exceeds one cycle, thereby adjusting signal skew within the same cycle.
In order to achieve the aforementioned object, according to the invention, in parallel signal transmission by using plural transmission lines, a predetermined synchronous cycle is executed with transmission of primary signals necessary for the operation of a circuit halted, and phase shifts between the signals on the respective transmission lines are detected by using a predetermined time as a reference. Thus, even when Adhere is a phase shift exceeding one cycle between the signals received through the transmission lines, the phase shift can be appropriately adjusted and the signal skew can be adjusted within the same cycle.
Specifically, the adjusting device of this invention for delay times between plural transmission lines comprises a signal output unit; plural transmission lines connected with the signal output unit for simultaneously transmitting an output signal of the signal output unit; a signal receiver unit for receiving signals on the plural transmission lines; plural timing adjusting means disposed on plural paths from the signal output unit through the plural transmission lines to the signal receiver unit for adjusting signal transmission delay times of the transmission lines; synchronous cycle setting means for setting a predetermined synchronous cycle; delay time detecting means for detecting delay times between the signals on the transmission lines simultaneously output from the signal output unit and received by the signal receiver unit within the synchronous cycle set by the synchronous cycle setting means; and control means for controlling the plural timing adjusting means on the basis of the delay times between the signals on the transmission lines detected by the delay time detecting means.
In one aspect of the adjusting device for delay times between plural transmission lines, the control means includes delay time determining means for determining delay times to be respectively inserted into the transmission lines which make the signal receiver unit simultaneously receive the signals on the transmission lines on the basis of the delay times between the signals on the transmission lines detected by the delay time detecting means; and delay value setting means for controlling the plural timing adjusting means so as to insert the delay times determined by the delay time determining means into the corresponding transmission lines.
In another aspect of the adjusting device for delay times between plural transmission lines, the synchronous cycle setting means sets the synchronous cycle at a predetermined time interval.
In still another aspect of the adjusting device for delay times between plural transmission lines, the signals are transmitted to the transmission lines with parity provided, and the synchronous cycle setting means detects a transmission error in a signal received by the signal receiver unit and sets the synchronous cycle when the transmission error is detected.
In still another aspect, a temperature sensor is disposed at least in one of the signal output unit, the signal receiver unit and the plural transmission lines, and the synchronous cycle setting means sets the synchronous cycle when the temperature sensor detects a temperature change exceeding a predetermined value.
In still another aspect, the synchronous cycle setting means sets the synchronous cycle by transmitting a synchronous signal to an additionally provided dedicated transmission line.
In still another aspect, the synchronous cycle setting means sets the synchronous cycle by fixing the signals simultaneously transmitted through the plural transmission lines at a predetermined potential level during a predetermined period.
In still another aspect, signal transmission between the signal output unit and the signal receiver unit is performed in accordance with a predetermined protocol, and the synchronous cycle setting means sets the synchronous cycle by outputting the protocol.
In still another aspect, the plural timing adjusting means respectively include plural delay devices and a selecting circuit for selecting a combination of the delay devices.
In still another aspect, the plural timing adjusting means are provided in the same number as the number of the plural transmission lines, with each timing adjusting means disposed on the corresponding transmission line.
In still another aspect, the delay time detecting means uses, as a reference, a signal on one transmission line received in the synchronous cycle by the signal receiver unit the last among the signals simultaneously output from the signal output means and received by the signal receiver unit, and detects delay times between the reference signal and the other signals on the other transmission lines.
In still another aspect, output of the output signal from the signal output unit is performed in accordance with a clock signal, and a period of the synchronous cycle set by the synchronous cycle setting means exceeds one cycle of the clock signal.
Alternatively, the method of this invention of adjusting delay times between plural transmission lines comprises the steps of setting a synchronous cycle as a cycle for synchronizing signals on plural transmission lines; simultaneously transmitting an output signal of a signal output unit to the plural transmission lines and receiving the signals on the plural transmission lines by a signal receiver unit in the synchronous cycle; detecting delay times between the signals on the transmission lines received by the signal receiver unit in the synchronous cycle; and adjusting delay times of the transmission lines on the basis of the detected delay times so that the signals on the transmission lines simultaneously output from the signal output unit are simultaneously received by the signal receiver unit.
In one aspect of the method of adjusting delay times between plural transmission lines, a period of the synchronous cycle exceeds one cycle of a clock signal.
In this manner, according to the invention, in parallel transmission of one or more signals by using plural transmission lines, a predetermined synchronous cycle is executed and the signals are simultaneously transmitted from a signal output unit to the plural transmission lines in the synchronous cycle. A signal receiver unit receives the signals through the transmission lines, and delay time detecting means detects the delay times between the signals received through the transmission lines. At this point, since the delay times between the signals transmitted through the transmission lines in the synchronous cycle are detected with the period of the synchronous cycle defined as a period exceeding one cycle of a clock signal (for example, plural cycles of the clock signal), even when the signal transmission delay time of any of the transmission lines is so long that it exceeds one cycle, the signals received through the plural transmission lines can be synchronized in the same cycle.